Asic Design Engineer Resume Examples Templates for Professional Advancement

Alex Ellison

Asic Design Engineer

[email protected] | (469) 203-1515 | Austin, Texas, USA

Profile

Asic Design Engineer with over 8 years of progressive experience in full-chip digital design, verification, and silicon bring‑up for high‑performance integrated circuits. Proven expertise in RTL coding using Verilog/SystemVerilog, UVM testbench development, and synthesis on advanced process nodes. Adept at partnering with physical design, timing, and backend teams to ensure on‑time tape‑out delivery under power, area, and timing constraints. Recognized for delivering robust ASICs used in networking, data‑center acceleration, and edge‑AI applications.

Strong leadership in mentoring junior engineers, fostering cross‑functional collaboration, and driving innovation through automated verification flows. Passionate about continuous learning, embracing cutting‑edge EDA methodologies, formal verification, and power‑optimized design techniques to improve design quality, reduce iterations, and ensure silicon success.

Education

Bachelor of Science in Electrical Engineering
University of Texas at Austin, Austin, TX
Graduated: May 2014

Master of Science in VLSI Systems
University of California, San Diego, CA
Graduated: December 2016

Licenses & Certifications

• Certified ASIC Design Engineer – IEEE (License No ASIC‑2022‑001)
• Advanced UVM Verification Methodology Certification – Mentor Graphics
• Low Power ASIC Design Strategies – Coursera Professional Certificate
• SystemVerilog and Formal Verification Training – Cadence
• Agile Project Management Certification – PMI‑ACP

Work Experience

Senior Asic Design Engineer
Cisco Systems, San Jose, CA
January 2020 – Present

• Lead RTL architecture and design for high‑speed switch ASIC targeting 7nm node, coordinating with micro‑architecture, timing, and physical‑design teams to meet performance targets.
• Spearheaded UVM testbench development covering 85% functional coverage within first 3 verification weeks, reducing simulation regressions by 30%.
• Implemented power‑aware coding and clock/tree gating techniques, achieving over 20% dynamic power reduction in key subsystems.
• Directed cross‑disciplinary team of 6 engineers through synthesis flow, ECO cycles, and timing closure, culminating in successful first‑pass silicon bring up.
• Integrated embedded configuration interfaces and debug hooks to enhance production test efficiency and field diagnostics capabilities.

Asic Design Engineer
Broadcom Inc., Irvine, CA
July 2016 – December 2019

• Designed data‑path and control‑logic blocks for high‑throughput network processors, meeting tight spec and timing targets under heavy resource constraints.
• Authored directed and random UVM testbench flows, identifying and correcting >200 RTL bugs before tape‑out.
• Coordinated with backend physical design to close multi‑corner static timing, delivering 10% better timing margin than required.
• Contributed to FPGA prototyping validation and post‑silicon debug using logic analyzers and JTAG, accelerating root‑cause analysis and bug fixes.
• Published internal design‑review documents and conducted training sessions on UVM best practices across the organization.

Skills

• RTL Design & Verification: Verilog, SystemVerilog, UVM, Formal Tools (JasperGold)
• Synthesis & Timing Closure: Synopsys DC, Cadence RTL Compiler, PrimeTime
• Simulation & Debug: VCS, QuestaSim, Verdi, SpyGlass linting
• Low‑Power Techniques: Multi‑Vt, power gating, clock gating, UPF
• FPGA Prototyping: Xilinx Vivado, Altera Quartus
• Script & Flow Automation: Python, TCL, Perl, Jenkins CI/CD
• Project Management: Agile workflows, Jira, Confluence, SVN/Git version control
• Cross‑functional Collaboration: Interfacing with physical, backend, firmware, and test teams

Languages

• English – Fluent (Professional Working Proficiency)
• Spanish – Intermediate (Conversational)
• Hindi – Native

Summary

A result‑driven Asic Design Engineer with proven expertise in delivering first‑silicon success through robust RTL implementation and comprehensive verification flows. Known for optimizing performance, reducing power, and ensuring high QOS in demanding ASIC environments. Skilled at mentoring teams, architecting complex design blocks, and driving innovation through automated methodologies and low‑power strategies.

Dedicated to excellence in semiconductor design, continuous upskilling, and collaboration across EDA flows and multi‑disciplinary teams. Passionate about shaping next‑generation ASICs in networking, edge compute, and AI hardware domains.

Extra‑Curricular Activities

Active member of the IEEE Solid‑State Circuits community, regularly presenting technical talks on formal verification and low‑power design. Led internal ASIC Hackathons to foster team innovation and evaluate emerging IP blocks in accelerated timelines.

Mentored university student teams for RTL competitions and chip‑design projects, bridging academic learning with practical industry expectations. Organized knowledge‑sharing sessions on system‑level debug techniques and design‑for‑test strategies.

Volunteered at high‑school STEM fairs, demonstrating FPGA‑powered robotics kits and explaining digital logic fundamentals to students. Conducted workshops on hardware testbench creation to inspire future engineers.

Courses

Completed advanced learning modules including Low‑Power ASIC Design Techniques, Formal Verification with JasperGold, and UVM Testbench Methodologies. Certified in system‑level verification, multiple process‑node synthesis flows, and dynamic power optimization—equipping me to handle complex ASIC challenges end‑to‑end.

Completed specialized online courses in RTL optimization for AI‑accelerators and hardware security in semiconductor design to stay current with market demands.

Internships

Engaged in summer internship at Texas Instruments, where I contributed to mixed‑signal design verification, exercise formal equivalence checks, and synthesized RTL blocks that supported ADC/DAC interfaces. Gained practical experience in chain flows and silicon validation testcases.

Internship at Qualcomm focused on RTL code generation for embedded network accelerators. Performed code coverage analysis, functional assertions, and regression automation—providing early detection of design flaws.

These experiences reinforced my design flow understanding and gave me hands‑on skills across practical design, validation, and testbench automation phases.

Other References

Available upon request—includes senior engineers and verification leads from Cisco, Broadcom, and academic supervisors who can attest to my ASIC design, verification, and project leadership capabilities.

Hobbies

Passionate about FPGA‑based robotics, open‑source hardware projects, and building custom compute boards at home. Regularly read technical journals on semiconductor architectures, attend local maker fairs, and enjoy mentoring hobbyist clubs.

Keep active through outdoor cycling and photography, which provides creative balance and visual discipline complementing my technical work.